Hardware Engineer : Hardware Engineer Digital Verification
Location : New Hampshire
Job ID : 253
Description
Design Verification Engineer for a 6-9 month contract to simulate a system of large scale FPGAs.
Responsibilities
Maintaining an existing System Verilog simulation environment and adding new features, as well as developing environments for future FPGAs. It also includes working with FPGA design engineers to define and implement the verification requirements, develop test plans and execute the test plans. Additional responsibilities include helping the development team improve the FPGA design and verification process.
Requirements
- Minimum of 5-10 years of design/verification experience
- Experience with Synopsys VCS tool suite including System Verilog and Vera
- Knowledge of IPv4, IPv6, SPI-4.2, CSIX, GMII/TBI, POSPHY Level 3, and/or PCI.
Posting Date : 07/27/2010
Job Type : Contract